Conventionally, front-side illuminated solid state image capture devices have been developed in which a multilayered interconnect layer is provided on the top face of a semiconductor substrate; and color filters and microlenses are provided on the multilayered interconnect layer. In the front-side illuminated solid state image capture device, photodiodes are formed in the surface layer portion of the semiconductor substrate; and transfer gates are formed in the multilayered interconnect layer. The photodiodes are formed of, for example, an n-type diffusion region partitioned into each of the pixels by a p-type barrier layer. Light incident on the semiconductor substrate from above via the microlens, the color filter, and the multilayered interconnect layer undergoes photoelectric conversion by the photodiode; and the electrons produced are read via the transfer gate.
The utilization efficiency of light for such a front-side illuminated solid state image capture device is low because the light entering from the outside is incident on the semiconductor substrate after passing through the multilayered interconnect layer. Therefore, the amount of light incident on the photodiode of each of the pixels decreases as the pixel size is reduced; and the sensitivity undesirably decreases. Also, the distance between the pixels decreases as the pixel size is reduced. Therefore, problems such as color mixing also may occur when light incident on one pixel undergoes diffused reflection by the metal interconnects in the multilayered interconnect layer and enters another pixel. Color mixing causes the resolution of color to decrease; and subtle color differences cannot be discriminated.
To solve such problems, back-side illuminated solid state image capture devices have been proposed in which light is incident on the bottom face side of the semiconductor substrate, i.e., the side where the multilayered interconnect layer is not provided (for instance, refer to JP-A 2003-31785 (Kokai)). The light utilization efficiency is high and the sensitivity is high for back-side illuminated solid state image capture devices because light entering from the outside is incident on the semiconductor substrate without passing through the multilayered interconnect layer.
Drawing out the interconnects from the multilayered interconnect layer is problematic for back-side illuminated solid state image capture devices. Considering the mounted configuration of solid state image capture devices, it is favorable to draw out the interconnects upward, i.e., to the side where light enters. Therefore, it is conceivable to make a large hole in the semiconductor substrate, expose the interconnect of the multilayered interconnect layer at the bottom of the hole, and perform wire bonding directly to the exposed interconnect via the hole.
However, in such a case, the wire bonding portion cannot be utilized as a marker for the positional alignment when forming the color filters on the semiconductor substrate. Therefore, when forming the color filters, an infrared ray is irradiated from the support substrate side; and the shadow of the uppermost interconnect layer due to the infrared ray passing through the support substrate, the multilayered interconnect layer, and the semiconductor substrate is identified and utilized as a marker.
However, in such a solid state image capture device, the positional alignment of the uppermost interconnect layer of the multilayered interconnect layer is performed using the interconnect layer therebelow as the reference; the positional alignment of the lowermost interconnect layer of the multilayered interconnect layer is performed using the contact as the reference; the positional alignment of the contact is performed using the gate electrode as the reference; and the positional alignment of the gate electrode is performed using an STI (shallow trench isolation) formed on the lower face of the semiconductor substrate as the reference. Accordingly, the positional alignment of the color filter is performed indirectly from the first reference of the STI via the gate electrode, the contact, the lowermost interconnect layer, one or more intermediate interconnect layers, and the uppermost interconnect layer to the color filter in this order. On the other hand, the positional alignment of the barrier layer partitioning the pixels also is performed using the STI as the reference.
Thus, the fluctuation is undesirably large because the relative positional relationship between the color filter and the barrier layer is determined indirectly by numerous components interposed therebetween. As a result, high integration of the pixels is difficult as the pixels are downscaled because it is difficult to position the boundary between the color filters in the region directly above the barrier layer. Although it is conceivable to independently form an alignment mark dedicated to the positional alignment of the semiconductor substrate, the number of processes would undesirably increase and the process costs of the solid state image capture device would undesirably increase greatly.